Joint Supply, Threshold Voltage and Sizing Optimization for Design of Robust Digital Circuits

In this paper, we describe a method for joint supply, threshold voltage and sizing optimization, in presence of uncertain transistor parameters, to obtain robust energy-delay optimal designs. We extend our previous work on robust transistor sizing, which accounted for the added delay caused by transistor variations by adding margins on each gate delay proportional to the estimated delay variability and using a “soft maximum” function to combine path delays at converging nodes [13], to optimize Vdd, and Vth values as well, and to include the cost of uncertainty in energy. Using posynomial analytic models to predict the means and variances of delay and energy, we create an optimization problem that can be efficiently solved via Geometric Programming. Monte-Carlo simulations on representative datapath circuits show that our heuristics to model uncertainty improve the resulting optimal energy-delay curves by roughly 10%.